Interconnect Controller micro-programmed to H1-OS
I always thought my peripherals have to be smart but not based on microcontroller (LSI) but in discrete logic such as Heritage / 1. There conceived, then, the idea of \u200b\u200bbuilding a "generic controller" based on simple FSM whose state tables would be stored in an array of diodes. Today
finally got ready to develop the idea and, surprisingly, the development led me to understand the meaning of "stored program machine." I did not get to a particular design but my driver, a satisfying intimate with the concept, which try to explain in what follows.
A MACHINE WITH PROGRAM STORED
The first time I read a computer manual legendary something like this: "This is a sequential, stored-program, digital parallel computer", I wondered if it is possible to construct a computer that is not all that, because a parallel sequential machine stored-program is the de facto structure of every computer from the time before my birth.
was not always so. The first-generation computers (1940s and early 50s) were serious, that is, the data inside is processed bit by bit. Ramington and Rand and IBM had established their respective markets (with this type of equipment) where he built a CRAY supercomputer whose power was amazing, among other factors, the fact of processing data in parallel ... as we do today.
What's "stored program", however, was established early. Even before the ENIAC manufactured in the United States the Colossus in England, Alan Turing had already captured the concept in theory and had introduced in his model of "universal machine." Later, Von Neuman EDVAC built its U.S. based on this principle. However, by that same date were built machines where the program and relapse data in separate reports, the most notable one that IBM built for Univercidad Harvard in 1944, based on relays. Today often speak of "Von Neuman" versus "Harvard" to refer to a given computer architecture. The first has dominated for decades but in this century we are breaking that pattern to move quickly toward concurrent processing.
VISTA COMPUTER AS A FINITE STATE MACHINE (FSM)
Imagine a Finite State Machine (FSM) whose state table is stored in a memory. The technology used (RAM, diode array, etc.) is not important now, the important thing is to imagine how it is structured the data it contains and how the WSF will use it.
The purpose of the machine is to use the WSF to assemble sequences. Each memory location is a step sequence. For each location, each bit represents an output signal. Most departures are "control signals" of the machine a few output bits representing the next state of the FSM, ie, the "address" the next step.
This arrangement would not get much further if there was no need to make decisions based on input data. What makes a computer, anyway? Running sequences ... and nothing else! The greatness of such sequences are not fixed but take different paths depending on the input data and intermediate results. And great is the fact that much of these "facts" are used to route the FSM, ie, are "instructions", the program itself: Software. That
is precisely the essence of the concept of "program track history": the program itself is an input element, as well as data, and based on them, it generates one or the other sequence, hence the need for storage with data in the same medium.
Another key concept in which I had not noticed until today: the decision making process (the next state of FSM) also depends Term Of established much earlier by intermediate results. This is the case of a negative number after a short, for example. In computers, this is usually noted in the "flag register (Register Flags.)
back to my FSM, let's split the state table (For better organization) as "sub-sequences" of 4 steps each. This has implications for addressing the table: the N bits of address, will feed the 2 less significant from a 2-bit counter whose input is fed, in turn, by a pulse train (clock). The N-2 bits used to address other subsequences.
I said before, for each location, a few bits of output represent the "next step" in the sequence. Say you are M bits, and connect them to address not only subsequences sequences, so that our FSM can contain up to 2 ^ M subsequences.
Returning to the comparison of my FSM with a computer, the "subsequences" can be seen as "instructions." The difference is that these are not in the same memory where data recycle but in separate memory, in a computer "microprogrammed" (as is common from IBM/360 to this day), this would be "micro-code" the machine and its memory call "micro-code storage."
But that's not all, in fact, the machine we have so far still does not work because it is not able to make decisions based on the input data (real data who reside in main memory).
For this to happen, we just have to add the outputs of which involved Flags Register in addressing the state table. We have already taken the first two bits for the subsequence, now take the following 4 and food from the Flags Register (assuming this is 4 bits).
The machine will, of course, records, and means for processing data (eg an ALU). The Flags tickets come from these circuits, ie, the flags are set or removed depending on intermediate results, as intended. MY PROPOSAL
My proposal consite in that with such little means, you can build a computing machine where the software resides "as data" in the same memory where data true, but as states of the FSM table in separate memory. In other words, the "software" of the machine would direct its "micro-code."
A machine that's capable of making decisions based on interim results due to the Flags Register and can, in principle, perform tasks as complicated as possible to "program" in a state table that is, in turn, likely to be built.
My intention, however, is not theoretical but practical. The work to be done by this machine is assumed to be simple enough to be programmed directly as "micro-code."
intend to take this technique to provide some (limited) Device Controllers intelegencia the Heritage / 1. These would be printed circuit boards housed in the control unit of each peripheral and mission consitiría to read / write a buffer from the media in question (tape, serial port, printer, etc.) as well as negotiate the attention of the CPU in accordance with interrupt architecture Heritage / 1. Being
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